In communication systems it is desirable to accurately transmit as much information as possible through a communication channel for a given amount of transmission power. One method of improving the bandwidth in a communication system is to encode the transmitted data with a forward error-correcting code (FEC). The FEC interleaves the data and generates parity data, which is combined with the interleaved data and transmitted through the communication channel. A receiver includes a decoder that uses the parity data to help recover the data. Whether the decoder successfully recovers the data depends on the depth of the interleaving, the amount of parity data, and the characteristics of noise in the communication channel.
Referring now to FIG. 1, a block diagram is shown of a communication system 10. A first transceiver 12-1 and second transceiver 12-2, collectively referred to as transceivers 12, communicate with each other via a communication channel 14. Transceivers 12 include respective physical layer modules (PHY) 16 that directly interface with communication channel 14. PHYs 16 communicate with FEC encoders 18 and FEC decoders 20. Hosts 22 generate and receive the data that is processed by FEC encoders 18, communicated via communication channel 14, and decoded by FEC decoders 20.
Encoders 18 may employ a FEC such as low-density parity check (LDPC) and/or concatenated codes such as turbo serial-concatenated convolutional codes. Encoders include first, or outer, encoders 26 that encode the data from hosts 22 according to a first codeword. Interleavers 28 interleave encoded data from outer encoders before communicating it to second, or inner, encoders 30. Inner encoders 30 encode the interleaved data according to a second codeword. Inner encoders 30 then communicate the encoded data to PHYs 16 to be transmitted.
Optimal decoding for LDPC and turbo coding is too complicated to be implemented practically. Iterative decoding therefore provides a practical alternative. Iterative decoding is a sub-optimal decoding algorithm with reasonable implementation complexity. Iterative decoding is also referred to as message-parsing since the received message data is parsed between two decoding subsystems.
Decoders 20 include first sub-systems 32 that receive the transmitted data from PHYs 16. First sub-systems 32 communicate decoded data to deinterleavers 34. First sub-systems 32 can also generate one or more signals that indicate how certain first sub-systems 32 are of the accuracy of the data that was sent to deinterleavers 34. Second sub-systems 38 receive the deinterleaved data from deinterleavers 34 and decode it. Second subsystems 38 can provide feedback, or soft result, 40 to outer decoders 32 to improve decoding accuracy.
Referring now to FIG. 2 a flow diagram is shown of data as it passes through first sub-systems 32 and second sub-systems 38. When encoders 18 employ one of the turbo codes, first sub-systems 32 represent first, or outer, decoders and second sub-systems 38 represent second, or inner decoders. When encoders 18 employ one of the LDPCs, first sub-systems 32 represent all check nodes and the second sub-systems 38 represent all bit nodes.
Data from PHYs 16 enter first sub-systems 32 to be decoded according to the second codeword. The partially decoded data is communicated to second systems 38 to be decoded according to the first codeword. Second subsystems 38 communicate the soft result to first sub-systems 32 for further decoding. This process repeats until second subsystems 38 generate hard results 42 that are communicated to hosts 22. The number of iterations through first-subsystems 32 and second sub-systems 38 can be predetermined based on a maximum bit error rate (BER) desired in the hard results 42.
Increasing the number of iterations reduces the BER, i.e. increases the accuracy of the decoded data. However, increasing the number of iterations increases a computational burden on decoders 20. In order to maintain decoding throughput with the higher number of iterations the computational throughput of decoders 20 must be increased. This can be achieved by increasing a clock frequency of decoders 20. It should be appreciated however that increasing clock frequencies introduces other issues. These issues include increasing power consumption and/or increasing design complexity due to smaller signal timing margins. There remains a need in the art for a method of increasing the decoding throughput of decoders 20.